The present invention relates to semiconductor processing equipment, and more particularly to carriers for holding a semiconductor wafer during chemical-mechanical planarization.
Semiconductor wafers are polished to achieve a smooth, flat finish before performing subsequent process steps that create electrical circuit layers on the wafer. Many systems in the prior art accomplish polishing by securing the wafer to a carrier, rotating the carrier and placing a rotating polishing pad in contact with the rotating wafer. The art is replete with various types of wafer carriers for use during this polishing operation. A common type of carrier is securely attached to a shaft which is rotated by a motor. A wet polishing slurry, usually comprising a polishing abrasive suspended in a liquid, is applied to the polishing pad. A downward polishing pressure was applied between the rotating wafer and the rotating polishing pad during the polishing operation. This system required that the wafer carrier and polishing pad be aligned perfectly parallel in order to properly polish the semiconductor wafer surface.
The wafer carrier typically was a hard, flat plate which did not conform to the surface of the wafer which is opposite to the surface being polished. As a consequence, the carrier plate was not capable of applying a uniform polish pressure across the entire area of the wafer, especially at the edge of the wafer. In an attempt to overcome this problem, the hard carrier plate often was covered by a softer carrier film. The purpose of the film was to transmit uniform pressure to the back surface of the wafer to aid in uniform polishing. In addition to compensating for surface irregularities between the carrier plate and the back wafer surface, the film also was supposed to accommodate minor contaminants on the backside of the wafer surface. Such contaminants could produce high pressure areas in the absence of such a carrier film. Unfortunately, the films were only partially effective with limited flexibility and tended to take a "set" after repeated usage. In particular, the set appeared to be worse at the edges of the semiconductor wafer.
Another adverse effect in using conventional apparatus to polish semiconductor wafers was greater abrasion in an annular region adjacent to the edge of the semiconductor wafer. This edge effect resulted from two main factors, assuming a uniform polishing velocity over the wafer surface, (1) pressure variation (from the nominal polish pressure) close to the edge area and (2) interaction between the polish pad and the edge of the semiconductor wafer.
This latter factor was due to the carrier pressure pushing the wafer into the polishing pad. Thus, the polishing pad was compressed beneath the wafer and expanded to its normal thickness elsewhere. The leading edge of the wafer was required to push the polishing pad downward as it rode over new sections of the pad. As a consequence, an outer annular region of each wafer was more heavily worn away and could not be used for electronic circuit fabrication. It is desirable to be able to utilize the entire area of the wafer for electronic circuit fabrication.
Yet another problem with using conventional apparatus to polish semiconductor wafers was slower removal rates of material in the vicinity of the wafer's center (an effect referred to by some in the art as "center slow"). More specifically, when removing thin film layers, such as oxide film layers, from the wafer, the resulting oxide thickness was greater near the center of the wafer, as opposed to the more peripheral areas of the wafer. The post Chemical Mechanical Polishing (CMP) oxide pattern on the wafer surface typically resembled a dome-like shape with the thickest portion of the oxide located near the center of the wafer. Therefore, there existed a need to provide an improved semiconductor wafer polishing apparatus including a wafer carrier head design that corrects the center slow problem, as well as the additional shortcomings noted above.